Ham Radio 2000/Ham Radio 2000.iso/ham2000/misc/logisy30/demos.txt

Text File | 1993-01-31 | 14KB | 279 lines

    Demonstrations for using logisym


            [ * These are intended as a tutorial on using LOGISYM * ]
            [ and not as a tutorial on the subject of digital logic ]


    1. First run:     Basic operation of the simulator, and a look at the
                      basic logic functions AND, OR, NOT, and  BUFFER, as
                      well as the unit delay model.

    2. Exclusive Or:  More about Logisym's controls and a demonstration of
                      an Exclusive Or gate built from  AND, OR, and NOT
                      logic gates.

    3. 4 to 1 MUX:    The use of function keys as input data to a circuit,
                      details on single step, and a demonstration of a
                      4 to 1 multiplexer.

    4. Arithmetic:    A simultaneous look at the half and full adders.

    5. 'Z' clocks:    Clock controls and a demonstration of the use and
                      versatility of the internal signals as inputs to
                      circuits.

    6. Flip flops:    Time base & Single step to observe detail and flow
                      of logic, featuring logisym's ability to accurately
                      simulate sequential logic circuits. Hazard states in
                      flipflops.



    1. First run

        If you have not done so, create a \LOGISYM directory on your
    hard disk and copy all of the logisym files to this directory.

        At the DOS prompt type the command line:

                 C:\LOGISYM > logisym andornot<CR>

        The first screen is the SHAREWARE and COPYRIGHT notice, read
    the notice and press <CR> to acknowledge and accept the terms
    specified. The next screen is the file select/load screen.

        Since you specified the file ANDORNOT.CKT on the command line,
    Logisym will not display a listing of the circuit files and will
    not prompt you to enter the files to be simulated. Next time try
    running Logisym without a circuit file on the command line.

        Logisym will begin to load and parse the file, reporting the
    number of logic probes, logic gates, and errors found. When
    finished, you are prompted to 'Press any key when ready', do so.

        You are now in the trace screen. Depending on the speed and
    architecture of your computer the trace may be flying by at an
    overwhelming rate, or crawling along at a snail's pace. Adjust
    the delay time by turning the DELAY knob in the lower right area
    of the screen, this is done by either pressing <y> to turn
    counter clockwise, or pressing <Y> to turn clockwise, or by
    clicking the left mouse button on '-' or '+'. Adjust the delay to
    minimum and then to maximum extremes, now adjust the delay so the
    trace takes between 5 and 15 seconds to cross the screen. This
    delay is passive and has no effect on the operation of the circuit.

        By this time a few trace screens may have passed, press <T> to
    turn AUTO TRIGGER off, a red square in braces: [■] indicates ON,
    empty braces: [ ] indicates OFF. When off the trace will stop at
    the end of the current screen and automatically go into PAUSE mode.

        Now take a close look at the timing chart generated by logisym.
    The yellow traces are internal clock signals, Z*, used as inputs to
    the circuit, the green traces are the outputs from logic gates defined
    in the circuit. The 1s and 0s on the right are the instantanious
    binary value of each trace.

        In this simulation the top trace is ZD, a bit from the eight bit
    up/down counter. Next is ZR, a bit from the four bit random data
    generator. Look at the gate outputs. The output from OA, an AND gate,
    is high only when both ZD and ZR are high. The output from OB, an OR
    gate, is high when either ZD or ZR are high. The output from OC, an
    inverter (sometimes called a NOT gate), is high only when its input,
    OB, is low. IA, a buffer, follows its input, OC, exactly.

        Notice several buffers are cascaded. Turn the TIMEBASE knob fully
    clockwise by pressing (uppercase)<B> or clicking the left mouse button
    on the '+' just below the knob, and press the <SPACEBAR> to proceed to
    the next trace screen. Now watch for an event that causes IA to change
    states, observe the delay in the signal as it is propagated through the
    other buffers. This is the 'unit delay', it has no defined time in the
    simulation but is representitive of a real delay that exists in all
    logic devices. The unit delay is the same (has the same value) for all
    logic functions in Logisym except for the RS, D, and JK flipflops. In
    the generic TTL inverter (part # 7404) this delay would be about 10
    nanoseconds.

        In this lesson you have learned how to use the BUTTONS and KNOBS
    that control many of logisym's functions. We have also reviewed the
    fundamental operations in which all logic functions are rooted. In the
    future adjust DELAY according to your needs, the speed of your computer
    and the TIMEBASE you are using.


    2. Exclusive Or

        At the DOS prompt type the command line:

                 C:\LOGISYM > logisym<CR>

        Press <CR> to transend the sharware and copyright notice. Observe
    the listing of files in the window at the bottom of the screen. At the
    prompt type XOR and press <CR> as below:

                 FILES  XOR<CR>

        Logisym should load XOR.CKT without error. Proceed to the trace
    screen by pressing any key.

        First turn the TIMEBASE fully counter clockwise by pressing <b> or
    clicking on the '-'. Now adjust the COUNTER so that there are sixteen
    complete cycles of ZB per trace screen. Adjust the RANDOM DATA, ZT, to
    either extreme, and observe the relative rates. Now adjust RANDOM DATA
    so there are about 10 to 20 transitions of ZT per screen.

        The gates labeled Xa - Xe are an exclusive or gate made up of AND,
    OR, and NOT functions. The output of the XOR is at the OR gate labeled
    XE. The exclusive or function is similar to the OR except that the
    condition where both inputs are true (high) has been eliminated. Thus
    the XOR gate is high (true) only when its inputs are different from
    one another: XE = 1 when ZB = 0 and ZT = 1, or ZB = 1 and ZT = 0.

        The gate LE is an internal XOR function, and is shown for comparsion.
    Note the output of LE is the same as XE with the exception of time. The
    gate LE is a single XOR function of one unit delay, whereas the XE has
    two to three units of delay, depending on the previous inputs to the
    gate.

        In this lesson we have observed the control of TIMEBASE, COUNTER
    frequency, and the rate of change of the RANDOM DATA. We have seen the
    effect of cumulitave unit delays in comparison to a single delay having
    the same logical function. As well as reviewed the operation of the
    exclusive or function.



    3. 4 to 1 mux

        Start Logisym and load the file MUX.CKT.

        At the trace screen, turn AUTO TRIGGER off, turn SINGLE STEP on,
    and turn the STEP MULTIPLIER, TIMEBASE, and RANDOM DATA fully clockwise.
    Press the <SPACEBAR> until the trace screen is at the end. Now press
    <SPACEBAR> again to start the next screen. The trace should cover 1/4 of
    the trace screen.

        Examine the first two inputs, labeled SELECT. These are controlled
    by the function keys on your keyboard. They both should be low (0). Now
    press <F1> to change ZI from low to high. The trace does not immedately
    show the change but the LOGICAL VALUE at the right of the screen does.
    ZI should now be high and ZJ low, Check the logical value to the right.
    Press <m> to place a MARKER. Press <SPACEBAR> to begin another set of
    traces. When the trace stops, press <F1> and <F2> to toggle both of the
    SELECT inputs. Place a MARKER and press the <SPACEBAR> again. When the
    trace stops, press <F1>, place another MARKER then press <SPACEBAR>.

        Examine the SELECT inputs from left to right, the binary values
    reflect a decimal count of 0, 1, 2, 3. Now look at the output MZ, while
    the SELECT inputs are 0, the output follows INPUT 0. While the SELECT
    inputs are equal to 1 the output follows INPUT 1, and so on.

        We have seen how to control data by way of the keyboard, and used
    the SINGLE STEP feature to allow us break points so we may have control
    over the operation of the circuit. We have also observed the operation
    of a 4 to 1 data selector (multiplexer).



    4. Arithmetic

        Start Logisym and load the files: HALFADDR.CKT and FULLADDR.CKT

                 C:\LOGISYM > logisym halfaddr fulladdr<CR>

        - or -

                 FILES  HALFADDR FULLADDR<CR>

        You now have two independant circuits loaded and running at the
    same time.

        Adjust the DELAY, TIMEBASE, and COUNTER so that you may analyze
    the operation of the half and full adders. Notice ZA, ZB, and ZC do
    not change relative to one another, they are all bits from the up/down
    counter controlled by the COUNTER knob.

        Practice using the features you have learned in the previous
    lessons. Analyze both circuits and verify their operations as binary
    adders.



    5. 'Z' clocks

        Start Logisym with the files: ZCOUNT.CKT, ZRAND.CKT, and ZRING.CKT

                C:\LOGISYM > logisym ZCOUNT ZRAND ZRING<CR>

        - or -

                FILES  ZCOUNT ZRAND ZRING<CR>

        First notice there are no green traces (gates), these are all
    internal clocks signals used to control logic circuits. An eight bit
    up/down counter, a four bit random data generator, and a four bit ring
    counter.

        Using the knobs, adjust the rates of each and observe the results.
    Notice the up/down counter, ZA - ZH, is counting up. Press <ALT><C>,
    or click the left mouse button on the up arrow to the left of COUNTER.
    The counter is now counting down. Repeat this proceedure for the ring
    counter, <ALT><R> or left mouse button on the arrow to the left of RING
    COUNTER.

        Adjust the TIMEBASE, COUNTER, RING COUNTER, and RANDOM DATA knobs
    fully clockwise. Examine the random data generator. Now press <ALT><D>,
    or click the left mouse button on the square to the left of RANDOM DATA.
    The square changes to an up arrow. Examine the random data again...
    there may now be 'spikes' in the data. That is, values may go from 0 to
    1 back to 0, or 1 to 0 back to 1. The middle state never holds its value
    for any period of time and can cause problems in some logic circuits.
    This control is called the RANDOM DATA LOW PASS FILTER. When on, SQUARE,
    the random data generator will not allow a change from 0 to 1 to 0, or
    from 1 to 0 to 1, the bit must hold its value for at lease one unit
    delay. When off, ARROW, the random data generator may produce these
    random spikes

        Quit logisym and restart it loading the file: ZKEY.CKT

        Eight straight lines of data... press any of the function keys,
    <F1> through <F8>, and observe the results. Try pressing <SPACEBAR>
    to put Logisym in PAUSE mode and press function keys to achieve the
    values you desire. Check these values to the right, LOGICAL VALUE,
    and press <SPACEBAR> again to release PAUSE mode.



    6. Flipflops

        Start Logisym with and load the file: RSFF.CKT

        The RS flip flop is usually the first sequential circuit most of
    us encounter. It is made of two cross coupled NAND gates, meaning one
    input to each is the output of the other. Unlike combinational circuits,
    a sequential circuit's response to an input is dependent on the previous
    inputs and the current state of the circuit. Often sequential circuits
    have one or more hazard states associated with them. That is a condition
    that may cause unexpected or unwanted results, outputs that are changing
    from 1 to 0 to 1 to 0 ...  this is called a 'race' condition. Adjust the
    TIMEBASE and COUNTER fully clockwise, then adjust the RANDON DATA to
    closely match the rate of the counter. Watch for both inputs to change
    from 0 to 1 at the same time, and observe the circuit's response. Repeat
    this proceedure while in SINGLE STEP mode, when it beings to 'race' press
    <K> to disable to clock signals. STEP the simulation a few times, the RS
    flipflop doesn't resolve its race condition. When disabled, all of the
    clock signals stop running and hold their current value until re-enabled,
    the function keys are always operational. Press <K> again to re-enable
    the clocks, and observe when and how the race condition is resolved.

        Repeat the above lesson using the D flipflop (DFF.CKT) and the JK
    flipflop (JKFF.CKT). Determine the hazard conditions for each circuit
    and how they are resolved. Try setting the TIMEBASE to maximum and STEP
    MULTILPIER to minimum and observe the transitions of each gate in the
    circuit while it is setting, resetting, and in a race condition.